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AR# 34884

MIG Virtex-6 DDR2/DDR3 - Simulation Debug


This section of the MIG Design Assistant focuses on Simulation Debug for the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


For a complete list of simulation debug steps for Virtex-6 DDR3/DDR2 designs please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Simulation Debug" section of UG406:

For steps on simulating the example design for Virtex-6 DDR3/DDR2 designs please refer to the "Getting Started"=>"Quick Start Example Design" section of UG406:

For information on why writes on the DDR interface contain more data than requested from the user interface, please see:
For information on Debugging issues with a User Design Simulation, please see:

Linked Answer Records

Associated Answer Records

AR# 34884
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG