The timing driven Place and Route does take some time to implement the design.
The run time also depends on the device; high run time is expected for a bigger device with less RAM size.
Below are some possible causes of high hold errors.
If clocks are brought in on CC (Clock Capable) pins and then routed to BUFGs.
There is no direct route from a CC pin to a BUFG, so this leads to a long delay in the clock route which leads to the hold errors.
You will need to move these clock inputs to GC (Global Clock) pins or change the buffers to BUFIO and/or BUFRs, depending on what you are clocking with these clocks.
- Period constraint on input clocks of BUFGMUX.
The output clock of BUFGMUX has two constraints, so please use a priority construct.
The input PERIOD constraints must be related for the PRIORITY keyword to impact the analysis correctly.
Here is the example syntax for using the priority keyword in ucf:
TIMESPEC "TS_Clk0" = PERIOD "clk0_grp" 10 ns HIGH 50% PRIORITY 2;
TIMESPEC "TS_Clk2X" = PERIOD "clk2x_grp" TS_Clk0 / 2 PRIORITY 1;
Note: Hold time violation could potentially be caused by great positive clock skew, which is caused by improper clock routing.