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AR# 34900

11.5 NGDBuild - "WARNING:ConstraintSystem:119..." on PIN location (LOC) constraints

Description

The followingwarningsare issuedduring Translate:

"WARNING:ConstraintSystem:119 - Constraint < net "xon_gen" LOC = AE9; >[./top_spaui_host_xaui.ucf(24)]: This constraint cannot be distributed fromthe design objects matching 'NET "xon_gen"' because those design objects do not contain or drive any instances of the correct type.

"WARNING:ConstraintSystem:203 - A target design object for the Locate constraint '< net "xon_gen" LOC = AE9; > [./top_spaui_host_xaui.ucf(24)]' could not befound and so the Locate constraint will be removed."

How can I solve this problem?

Solution

These warnings are issued because the "xon_gen" pin does not drive an IBUF, but drives the FPGA fabric directly (as shown in the following screenshot from the PlanAhead tool). NGDBuild does not find the IBUF component and issues the warnings.

Tosolve this problem, make sure the I/O buffer insertion is enabled globally, or for the specific pin, when you synthesize the design.

  1. Globally enableI/O buffer insertion.
    • For XST, go to Synthesis Properties -> Xilinx Specific Options -> check "Add I/O Buffers" in Project Navigator or use "-iobuf YES" in commend line.
    • For Synplify Pro, go to Implementation Options -> Device tab -> uncheck "Disable I/O Insertion"
  2. Selectively enableI/O buffer insertion.
    • For XST, use "buffer_type" constraint. Please refer to XST User Guide.
    • For Synplify Pro, refer to (Xilinx Answer 4508).
AR# 34900
Date Created 04/05/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
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