^
Advanced Search

AR# 34903 MIG Virtex-6 DDR2/DDR3 - PHY-Like Controller Responsibilities

Description

This section of the MIG Design Assistant focuses on the "PHY-Like" responsibilities that are handled by the Virtex-6 DDR2/DDR3 design's Controller. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The Memory Controller design executes the following "PHY-like" responsibilities that are pertinent for proper operation:

(Xilinx Answer 34355) - DDR3 - JEDEC Specification - ZQ Calibration
(Xilinx Answer 34480) - DDR2/DDR3 Periodic Reads

Revision History
09/20/12- Updated link

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34906 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Controller Responsibilities N/A N/A
34480 MIG Virtex-6 DDR2/DDR3 - Phase Detection Circuit and Periodic Reads N/A N/A
34282 MIG Design Assistant - Virtex-6 Core Functionality N/A N/A
34355 MIG Virtex-6 DDR3 - JEDEC Specification - ZQ Calibration N/A N/A
51233 Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist N/A N/A

Actions

AR# 34903
Date Created 05/20/2010
Last Updated 02/15/2013
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG
Feed Back