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Xilinx Configuration Solution Center


 

The Configuration Solution Center is available to address all questions related to Configuration.

Whether you are starting a new Configuration Scheme or troubleshooting a Configuration related problem, use the Configuration Solution Center to guide you to the right information.

Other useful Configuration References:

  • Xilinx Configuration Forum: A board to discuss Xilinx Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, etc.
    This board will also include iMPACT and Vivado Device Programmer software related topics.
  • Design Hubs: Provide introductory material, key concepts, and FAQs on subjects like Partial Reconfiguration, Programming & Debug

Design Assistant

Xilinx Configuration Solution Center - Configuration Design Assistant

The following answer records cover current known issues as well as commonly asked questions related to configuration.

Note: This answer record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)

The Xilinx Configuration Solution Center is available to address all questions related to Configuration.


UltraScale and UltraScale+

(Xilinx Answer 66570)UltraScale Architecture Soft Error Mitigation Controller - Guidance for testing with error injection
(Xilinx Answer 63609)UltraScale and UltraScale+ Soft Error Mitigation Controller - Release Notes
(Xilinx Answer 63857)UltraScale External DONE pull-up recommendation

7 Series

(Xilinx Answer 57045)Design Advisory for Artix-7, Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration
(Xilinx Answer 44942)Virtex-7, Kintex-7, Artix-7 FPGA Configuration - BUSY Pin Removal
(Xilinx Answer 42543)7 Series Configuration - Fallback is disabled by default; Multiboot image does not fallback
(Xilinx Answer 43174)7 Series - PROGRAM_B pin held Low prior to power-up does not delay configuration
(Xilinx Answer 42544)7 Series Configuration - When Fallback is enabled, the device status register is always cleared after a failed configuration attempt
(Xilinx Answer 41782)7 Series - Why is there no longer a recommendation for Thevenin termination on the CCLK pin for configuration?
(Xilinx Answer 41298)SelectIO 7 Series - What power rail supplies the dedicated configuration pins? (MODE pins, JTAG pins etc.)
(Xilinx Answer 47449)Virtex-7 XC7VX690T Initial Engineering Sample (IES) - iMPACT Verify fails and Configuration Readback does not work correctly unless PCIe DRP is instantiated
(Xilinx Answer 50489)7 Series - ERROR:Bitgen:145 - Why are RS0 and RS1 pins persisted if the design is not using Multiboot and the BitGen ConfigFallback option is not set?
(Xilinx Answer 51337)7 Series - How can I work around the Fallback limitation for 32-bit addressing in SPI mode?
(Xilinx Answer 51473)7 Series - Which dual mode configuration pins do the "BitGen -g persist:yes" option apply to on 7 Series devices?
(Xilinx Answer 52626)7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output
(Xilinx Answer 53903)7 Series - When the Readback CRC and AES bistream encryption features are both enabled, the Readback CRC requires the ICAP to be included in the design to function
(Xilinx Answer 44635)7 Series - EMCCLK considerations to ensure the FPGA completes the startup sequence

Older Architecture

(Xilinx Answer 32653)Spartan-3/-3E/-3A/-3AN/-3DSP Families - I/O's glitch during power up or down, or a PROG_B pulse
(Xilinx Answer 33575)Spartan-6 FPGA - JTAG Configuration Setup For Designs Using GTPs


Vivado Hardware Manager

(Xilinx Answer 69758)Vivado: How do I get a standalone version of Vivado Programming Tools to run in the lab?
(Xilinx Answer 66440)Vivado - Linux OS - Digilent and Xilinx USB cable installation check
(Xilinx Answer 59128)Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite?
(Xilinx Answer 52881)Configuration - BitStream Encryption - How to create and program an encrypted bitstream
(Xilinx Answer 54939)2013.x Vivado, 14.5/6 iMPACT, Flash Programming, ChipScope, PromGen - I do not see iMPACT or ChipScope when I install the Vivado 2013.1 tools
(Xilinx Answer 61312)Non IEEE 1149.3 compliant devices are not recognized in the JTAG chain
(Xilinx Answer 66954)Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected
(Xilinx Answer 65328)2015.3 Vivado Device Programmer - UltraScale - Direct configuration of RSA Authenticated bitstreams not supported
(Xilinx Answer 55660)Vivado Constraints - How to resolve DRC Warning:[DRC 23-20] Rule violation (CFGBVS-1) Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design
(Xilinx Answer 58406)2013.2 Hardware Manager - ERROR:[Labtools 27-1974] Mismatch between the design programmed into the device XC7K325T_0 and the probes file

iMPACT

(Xilinx Answer 47890)14.x iMPACT - Known Issues for the iMPACT 14.x tools
(Xilinx Answer 476)PROMGen - Description of PROM/EEPROM file formats: MCS, EXO, HEX, and others
(Xilinx Answer 52881)Configuration - BitStream Encryption - How to create and program an encrypted bitstream
(Xilinx Answer 23174)PROMGen - Is it possible to convert an MCS file into a BIN (HEX or EXO) file?
(Xilinx Answer 16996)Vivado/ISE - How does the bitstream compress option work (MFWR - Multiple Frame Write Register)? How much compression will be achieved?
(Xilinx Answer 14468)BitGen - Explanation of output files (.bit, .rbt, .bgn, .drc, msk, .ll, .nky, .rba, .rbb, .rbd, .msd, .bin)
(Xilinx Answer 36210)PROMGen - How can file formats be changed or have files bitswapped?
(Xilinx Answer 34599)iMPACT - Status Register read shows all '0'
(Xilinx Answer 8902)iMPACT - What is "IDCODE looping?"
(Xilinx Answer 11857)iMPACT - What is "Initialize Chain"?
(Xilinx Answer 24024)iMPACT - How can the data from the Status Register be used to debug configuration issues?
(Xilinx Answer 34909)iMPACT - What do the different bits in a Status Register Read and BOOTSTS mean?
(Xilinx Answer 13529)iMPACT - "ERROR: iMPACT:583) - '2' The IDCODE read from the device does not match the IDCODE in the BSDL file"
(Xilinx Answer 44237)13.3 - BitGen - 7 Series - DonePipe option is now enabled by default


Cables

(Xilinx Answer 54381)Xilinx Programming Cables - Platform Cable USB and Parallel Cable IV - Driver install FAQ
(Xilinx Answer 54382)Digilent Programming Cables - Driver Install FAQ
(Xilinx Answer 66440)Vivado - Linux OS - Digilent and Xilinx USB cable installation check
(Xilinx Answer 59128)Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite?
(Xilinx Answer 35924)10.1, 11.x - ISE - Installation of Cable Drivers for ISE 10.1, 11.x on Windows 7
(Xilinx Answer 20429)Platform Cable USB - Frequently Asked Questions (FAQs)
(Xilinx Answer 44397)13.x/14.x iMPACT - Cable Driver Installation - Installation passes on Windows 7 but the Jungo driver Windrvr6 does not operate or appear in the device manager
(Xilinx Answer 64361)Configuration - Cable Driver - The driver of JTAG USB cable cannot be installed in Ubuntu.
(Xilinx Answer 54382)Digilent Programming Cables - Driver Install FAQ
(Xilinx Answer 29310)Platform Cable USB/USB-II - Libusb Driver support available on Linux
(Xilinx Answer 31397)Platform Cable USB - "A service installation section in this INF is invalid..."
(Xilinx Answer 30184)iMPACT - "WARNING:iMPACT:923) - Cannot find cable, check cable setup" / "Cable connection failed"


Generic Configuration Solution

(Xilinx Answer 11433)JTAG - Do the JTAG pins need external pull-ups? What should I do with unused JTAG pins?
(Xilinx Answer 3203) JTAG - General description of the TAP Controller states
(Xilinx Answer 16832)JTAG - What is a JTAG scan bridge, scan path linker, or JTAG multiplexer/JTAG mux?
(Xilinx Answer 42128)FPGA Configuration - How many clock cycles should I apply to CCLK after DONE has gone High?
(Xilinx Answer 50163)Tandem PROM - What signals are added to my design by using the Tandem PROM solution?
(Xilinx Answer 40212)Configuration FPGA Multiboot - Can I multiboot a master and slave device at the same time in a parallel or slave daisy chain?

Documentation

Xilinx Configuration Solution Center - Configuration Documentation

Please refer to the following documentation when using Xilinx Configuration Solutions.

Note: This Answer Record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)


UltraScale and UltraScale+

(UG570)UltraScale Architecture Configuration User Guide
(UG575)Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts ProductSpecification
(UG974)UltraScale Architecture Libraries Guide
(UG835)Vivado Design Suite Tcl Command Reference Guide
(DS922)Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
(DS923)Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
(DS892)Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
(DS893)Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
(XAPP1280)UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3
(XAPP1257)MultiBoot and Fallback with SPI Flash in UltraScale FPGAs
(XAPP1233)SPI Configuration and Flash Programming in UltraScale FPGAs
(XAPP1230)Configuration Readback Capture in UltraScale FPGAs
(XAPP1220)UltraScale FPGA BPI Configuration and Flash Programming
(XAPP1188)FPGA Configuration from SPI Flash Memory using a Microprocessor
(XAPP1267)Using Encryption and Authentication to Secure an UltraScale/UltraScale+ FPGA Bitstream
(XAPP1283)Internal Programming of BBRAM and eFUSEs
(XAPP1282)UltraScale FPGA Post-Configuration Access of Parallel NOR Flash Memory using STARTUPE3
(XAPP1232)Bitstream Identification with USR_ACCESS using the Vivado Design Suite
(XAPP1191)SPI Flash Programming including Bitstream Revision Selection
(XAPP1098)Developing Tamper-Resistant Design with UltraScale and UltraScale+ FPGAs

7 Series

(UG470)7 Series FPGAs Configuration User Guide
(UG475)7 Series FPGAs Packaging and Pinout Product Specification
(UG953)7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide
(UG835)Vivado Design Suite Tcl Command Reference Guide
(DS181)Artix-7 FPGA Data Sheet: DC and AC Switching Characteristics
(DS182)Kintex-7 FPGA Data Sheet: DC and AC Switching Characteristics
(DS183)Virtex-7 FPGA Data Sheet: DC and AC Switching Characteristics
(XAPP1260)eFUSE Programming on a Device Programmer
(XAPP1247)MultiBoot with 7 Series FPGAs and SPI
(XAPP1246)MultiBoot with 7 Series FPGAs and BPI
(XAPP1239)Using Encryption to Secure a 7 Series FPGA Bitstream
(XAPP1232)Bitstream Identification with USR_ACCESS using the Vivado Design Suite
(XAPP1188)FPGA Configuration from SPI Flash Memory using a Microprocessor
(XAPP1179)Using Tandem Configuration for PCIe in the Kintex-7 Connectivity TRD
(XAPP1084)Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series FPGAs
(XAPP1081)QuickBoot Method for FPGA Design Remote Update
(XAPP733)Applying MultiBoot and the LogiCORE IP Soft Error Mitigation Controller
(XAPP587)BPI Fast Configuration and iMPACT Flash Programming with 7 Series FPGAs
(XAPP586)Using SPI Flash with 7 Series FPGAs
(XAPP583)Using a Microprocessor to configure 7 Series FPGAs via Slave Serial or Slave SelectMAP Mode
(XAPP538)Soft Error Mitigation Using Prioritized Essential Bits
(XAPP497)Bitstream Identification with USR_ACCESS

Older Architectures

(Xilinx Answer 37249)Xilinx Configuration Solution Center - Documentation - Older Architectures


Vivado Hardware Manager

(UG908)Vivado Design Suite User Guide: Programming and Debugging
(UG835)Vivado Design Suite Tcl Command Reference Guide
(UG909)Vivado Design Suite User Guide: Partial Reconfiguration
(UG947)Vivado Design Suite Tutorial: Partial Reconfiguration
(UG936)Vivado Design Suite Tutorial: Programming and Debugging
(UG949)UltraFast Design Methodology Guide for the Vivado Design Suite


iMPACT & Cables

iMPACT Help
(UG344)USB Cable Installation Guide
(DS300)Platform Cable USB Product Specification
(DS593)Platform Cable USB II Data Sheet


Note: When reviewing any of the documentation in this Xilinx Answer Record, ensure that the most recent version is being reviewed.


Design Advisories

Xilinx Configuration Solution Center - Configuration Design Advisories

The Configuration Design Advisory Answer Records (DAARs) are created for issues that are important to designs currently in progress, and you can select them to be included in the Xilinx Alert Notification System.

Note: To update your Xilinx Alert Notification Preferences, go to: https://www.xilinx.com/support/myalerts.

This Answer Record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)


UltraScale and UltraScale+:

For a comprehensive list on Design Advisories for UltraScale FPGAs, please refer to the Master Answer Record links below

 

(Xilinx Answer 61598) Design Advisory Master Answer Record for Kintex UltraScale FPGAs
(Xilinx Answer 61930) Design Advisory Master Answer Record for Virtex UltraScale FPGAs

 

UltraScale and UltraScale+:

 

Design Advisories Alerted on April 10th, 2017
(Xilinx Answer 68832) Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)
Design Advisory Alerted on December 19th, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 1st, 2016
(Xilinx Answer 68006) Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly
Design Advisory Alerted on December 21st, 2015
(Xilinx Answer 65792) Design Advisory for UltraScale RSA Authentication - UltraScale devices that use RSA authentication will fail bitstream authentication when smaller configuration interface widths are used.
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGA

 

7 Series:

For a comprehensive list of Design Advisories for 7 Series FPGAs, please refer to the Master Answer Record links below

(Xilinx Answer 42944) Design Advisory Master Answer Record for Virtex-7 FPGAs
(Xilinx Answer 42946) Design Advisory Master Answer Record for Kintex-7 FPGAs
(Xilinx Answer 51456) Design Advisory Master Answer Record for Artix-7 FPGAs

 

Virtex-7 Configuration Specific Design Advisories:

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisories Alerted on November 5, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
Design Advisories Alerted on August 20, 2012
(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices

 

Kintex-7 Configuration Specific Design Advisories

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisories Alerted on April 3, 2013
(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices
Design Advisories Alerted on November 5, 2012
(Xilinx Answer 50906) Updated Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices; updated for 14.3/2012.3 release
Design Advisories Alerted on October 29, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
Design Advisories Alerted on October 22, 2012
(Xilinx Answer 50617) Updated the bitstream compatibility section in the Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceiver
Design Advisory Alerted on October 17, 2011
(Xilinx Answer 44421) Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage

 

Artix-7 Configuration Specific Design Advisories

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on October 31st, 2016
(Xilinx Answer 68006) Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisory Alerted on August 26, 2013
(Xilinx Answer 57045) Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration
Design Advisory Alerted on October 29, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

 

Older Architectures

For a comprehensive list on Design Advisories for 6 Series FPGAs, please refer to the Master Answer Record links below:

(Xilinx Answer 34565) Design Advisory Master Answer Record for Virtex-6 FPGA
(Xilinx Answer 34856) Design Advisory Master Answer Record for Spartan-6 FPGA

 

Virtex-6 Configuration Specific Design Advisories

Design Advisory Alerted on August 13, 2012:
(Xilinx Answer 51145) Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning
Design Advisories Alerted on August 8, 2011:
(Xilinx Answer 42682) Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
Design Advisories Alerted on July 11, 2011:
(Xilinx Answer 41821) Design Advisory for Virtex-6 FPGA - BitGen Option -g Next_Config_Addr: Default Value Changed
Design Advisories Alerted on July 6, 2011:
(Xilinx Answer 42682) Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
Design Advisories Alerted on October 18, 2010:
(Xilinx Answer 38134) Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration

 

Spartan-6 Configuration Specific Design Advisories

Design Advisory Alerted on June 19, 2013
(Xilinx Answer 56363) Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured
Design Advisory Alerted on April 02, 2013
(Xilinx Answer 55037) Design Advisory for Spartan-3A and Spartan-6: After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered spurious failures might be flagged in Readback CRC
Design Advisory Alerted on November 19, 2012:
(Xilinx Answer 52716) Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces
Design Advisories Alerted on March 01, 2011:
(Xilinx Answer 40387) Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration
(Xilinx Answer 40818) Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately turned on in BitGen for Spartan-6 FPGA inputs
Design Advisory Alerted on December 13, 2010:
(Xilinx Answer 39582) Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin can not be User I/O
Design Advisory Alerted on November 15, 2010:
(Xilinx Answer 38733) Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

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