The MIG 7 series and Virtex-6 DDR2/DDR3 design includes a highly efficient Reordering Memory Controller. This section of the MIG Design Assistant focuses on the Reordering Memory Controller of the MIG 7 series and Virtex-6 FPGA DDR3/DDR2 designs. Please select from the options below to find information related to your specific question.
Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For information on the controller signals and parameters for the MIG 7 series and Virtex-6 FPGA DDR3/DDR2 design, see:
(Xilinx Answer 34923) - MIG Virtex-6 Controller Signal and Parameter Description
(Xilinx Answer 51914)-MIG 7 SeriesGenerated RTL Parameter, UCF Constraint, and Signal Descriptions
For information on the controller responsibilities for the MIG 7 series and Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34906) - Controller Responsibilities
For information on the MIG 7 series and Virtex-6 DDR3/DDR3 controller architecture/design, see:
(Xilinx Answer 36511) - Controller Architecture Design
For information on the controller interfaces of the MIG 7 series and Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34926) - Controller Interfaces