UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34909

iMPACT - What do the different bits in a Status Register Read and BOOTSTS mean?

Description


What does each bit of STAT register and BOOTSTS register mean?
How do you use them to debug configuration issues?
Formore iMPACT Error Articles and other Configuration Related Articles, see (Xilinx Answer 34104)

Solution

Status Register (STAT)

The Status Register indicates the value of numerous global signals. It contains the current status of the configuration process and is independent of the configuration methods. Bits in the status register will be initialized when PROG_B or power is pulsed.

The register can be read through the SelectMAP or JTAG interfaces from any Virtex or Spartan family devices.

Below is information regarding each bit in the status registers of Virtex-6, Virtex-5, Spartan-6 and Spartan-3A.

CRC ERROR (Virtex-6, Virtex-5, Spartan-6, Spartan-3A)

Power-Up State: "0"

Post-Config State:

"1" - The bitstream failed the CRC checking. INIT_B will go low when CRC errors occur (unless JTAG configuration is being used). CRC errors are typically due to clocking or SI issues on the board. If a CRC error occurs, try slowing down the configuration speed, or investigating the SI characteristics of the configuration signals (in particular, the clock line).

"0" - The bitstream passed the CRC checking. A "0" also can be the situation that the device failed to perform CRC checking (e.g. missed the Sync Word). Besides, in Virtex/E and Spartan-II/E, as the CRC only checked twice (just prior to last configuration frame and at the very end of configuration), double-clocking or SI issues could cause frame errors to lose the CRC checking commands, that would not be indicated by INIT_B as well.

DECRYPTOR ERROR (Virtex-6) / Decryptor security set (Virtex-5) / DECRYPTOR ENABLE (Spartan-6)

Power-Up State: "0"

Post-Config State:

"1" - Decryptor security set.

"0" - Decryptor security not set.

PLL LOCK STATUS (Virtex-6) / DCM locked (Virtex-5, Spartan-3A) / DCM LOCK STATUS (Spartan-6)

This bit is a logical AND function of all MMCM/DCM LOCKED signals. Unused MMCM/DCM LOCKED signals = 1.

Power-Up State: "1"

Post-Config State:

"1" - All MMCM/DCM were locked in the specified phase of the Startup sequence. If BitGen option 'Wait for PLL Lock (Output Event)' was set to 'No Wait', this bit would flag "1" as well.

"0" - One or more MMCM/DCM failed to lock and the Startup sequence hanged. First, remove this option 'Wait for PLL Lock (Output Event)' and try the files again to ensure that this is the problem. Next, analyze why the DCMs do not lock.

DCI MATCH STATUS (Virtex-6) / DCI matched (Virtex-5)

This bit is a logical AND function of all the MATCH signals (one per bank). If no DCI I/Os are in a particular bank, the bank's MATCH signal =1.

Power-Up State: "1"

Post-Config State:

"1" - All DCI I/Os were matched in the specified phase of the Startup sequence. If BitGen option 'Wait for DCI Match (Output Event)' was set to 'NoWait', this bit would flag "1" as well.

"0" - DCI did not match and the Startup sequence hanged. First, remove this option 'Wait for DCI Match (Output Event)' and try the files again to ensure that this is the problem. If this resolves the issue, the DCI matching issues will also need to be addressed.

END OF STARTUP (EOS) STATUS (Virtex-6) / End of startup signal from Startup block (Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - The Startup sequence (0~7 phases, EOS is the last phase) has finished.

"0" - Startup hangs or the device does not enter into Startup stage. Check other status bits to locate the configuration errors.

GTS_CFG_B STATUS (Virtex-6, Spartan-6) / status of GTS_CFG_B (Virtex-5, Spartan-3A)

Power-Up State: "0"

Post-Config State:

"1" - The Startup sequence has gone through the "Enable Output" phase and all I/Os behave as configured.

"0" - The Startup sequence is not finished and all I/Os are still hold in High-Z state. GHIGH and the CRC bits should be checked.

GWE STATUS (Virtex-6, Spartan-6) / status of GWE (Virtex-5, Spartan-3A)

Power-Up State: "0"

Post-Config State:

"1" - The Startup sequence has gone through the "Release Write Enable" phase, FFs and block RAM are write enabled.

"0" - The Startup sequence is not finished, FFs and block RAM are still held un-writable. GHIGH and the CRC bits should be checked.

GHIGH STATUS (Virtex-6, Spartan-6) / status of GHIGH (Virtex-5, Spartan-3A)

Power-Up State: "0"

Post-Config State:

"1" - The device has properly received its entire configuration data stream. The device is ready to enter the Startup sequence.

"0" - The device does not receive the entire configuration data stream.

MODE PIN M [0/1/2] (Virtex-6) / value of MODE pin M0/1/2 (Virtex-5, Spartan-3A) / MODE PIN M [0/1] (Spartan-6)

These bits are the status of the Mode pins. They are sampled on the rising edge of INIT_B and determine the configuration mode of the device. The configuration mode will not affect the functionality of the JTAG pins, which are always available regardless of the mode set. Always double check the Mode pins settings if configuration fails.

INIT_B INTERNAL SIGNAL STATUS (Virtex-6)/ Internal signal indicates when housecleaning is completed (Virtex-5)

Internal signal indicating whether initialization has completed and the device is ready to be configured.

Power-Up State:

"0" - Initialization has not finished. Check whether the power rails are valid and stable; and whether INIT_B pin or PROG_B pin is held low externally

"1" - Initialization finished

INIT_B PIN (Virtex-6)/ Value driver in from INIT pad (Virtex-5)/ INIT_B PIN (Spartan-6)/ value of CFG_RDY (INIT_B) (Spartan-3A)

This bit reflects the value on the external INIT_B pin.

Power-Up State: "1"

Post-Config State:

"1" - No CRC errors.

"0" - CRC errors are detected or the Startup sequence has completed as this pin becomes a User I/O in some devices. Check GHIGH, GWE, GTS and DONE to confirm this.

DONE INTERNAL SIGNAL STATUS (Virtex-6)/ Internal signal indicates that chip is configured (Virtex-5)

This bit is the value of the internal DONE signal.

Power-Up State: "0"

Post-Config State:

"1" - The internal DONE signal has been released and configuration is successful. If this bit is set and the device is not operational, check GTS and GWE to see if Startup has completed.

There are three exceptional scenarios where GHIGH will be "0" while DONE is "1": first, wrongly configure the device with a Debug bitstream. Second, program a single FPGA through a flash/PROM which contains a MCS file actually for a daisy chain. In both cases the LOUT command embedded in the configuration files makes DONE becomes "1" but the device cannot work. Third, program an encrypted bitstream into a device without programming the key file into it.

"0" -Configuration failed. Check other status bits to locate the reason of the failure.

DONE PIN (Virtex-6, Spartan-6)/ Value of DONE pin (Virtex-5)/ DONEIN input from Done Pin (Spartan-3A)

This bit reflects the value on the external DONE pin.

Power-Up State: "0"

Post-Config State:

"1" - Configuration is finished successfully.

"0"- Configuration failed. Check other status bits to locate the reason of the failure. This can occur if the DONE pin pull-up resistor is not strong enough and DONE pin does not go high within one clock cycle. This bit can be "0" if DONE pin is held low externally (internal DONE signal of Virtex-6 or Virtex-5 has been released). (e.g., hold the DONE pins of the upstream devices in a daisy chain to wait for the downstream devices to finish their data stream loading and then start up together.)

IDCODE ERROR (Virtex-6, Spartan-6)/ Indicates when ID value written does not match chip ID (Virtex-5)/ IDCODE not validated while writing FDRI (Spartan-3A)

Power-Up State: "0"

Post-Config State:

"1" - Attempt to write to FDRI without successful DEVICE_ID check.

"0" - IDCODE check passed.

SECURITY ERROR (Virtex-6)/ Decryptor error Signal (Virtex-5) /DECRYPTION ERROR (Spartan-6)

A FDRI write attempted before or after decrypt operation.

Power-Up State: "0"

Post-Config State:

"1" - No DEC_ERROR.

"0" - DEC_ERROR.

SYSTEM MONITOR OVER-TEMP ALARM STATUS (Virtex-6, Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" : System Monitor detects over-temp alarm.

"0" : Normal configuration.

CFG STARTUP STATE MACHINE PHASE [20:18] (Virtex-6)/ startup_state[20/19/18] CFG startup state machine(Virtex-5)

The three bits are the status of CFG startup state machine (0 to 7).

Power-Up State: "000"

Post-Config State:
Phase 0 = 000
Phase 1 = 001
Phase 2 = 011
Phase 3 = 010
Phase 4 = 110
Phase 5 = 111
Phase 6 = 101
Phase 7 = 100

SPI FLASH SELECT PIN FS [2/1/0] (Virtex-6)/ SPI Flash Type [24/23/22] Select (Virtex-5)/ value of VSEL pin 2/1/0(Spartan-3A)

SPI flash read command selection FS [2:0]:
000: 0xFF
001: RCMD [7:0]
010: 0x52
011: Reserved
100: 0x55
101: 0x03
110: 0xE8
111: 0x0B

CFG BUS WIDTH DETECTION (Virtex-6) /CFG bus width auto detection result (Virtex-5)

CFG bus width auto detection result. If ICAP is enabled, this field reflects the ICAP bus width after configuration is done.

Power-Up State: "00"

Post-Config State:
00: x1
01: x8
10: x16
11: x32

HSWAPEN PIN (Virtex-6, Spartan-6)

This bit reflects the HSWAPEN pin status.

EFUSE BUSY STATUS (Virtex-6)/ Indicates that efuse logic is busy (Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - efuse logic is busy.

"0" - Normal configuration.

E-fuse program voltage available (Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - E-fuse program voltage available.

"0" - does not detect E-fuse voltage.

BPI address wrap around error (Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - BPI address wrap around error detected in BPI configuration.

"0" - No warp around error detected.

IPROG pulsed (Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - IRPOG is pulsed.

"0" - Normal configuration.

read back crc error(Virtex-5)

Power-Up State: "0"

Post-Config State:

"1" - Readback CRC error detected.

"0" - No readback CRC error detected.

SUSPEND STATUS (Spartan-6)

This bit reflects the device Suspend status.

FALLBACK STATUS (Spartan-6)

Power-Up State: "0"

Post-Config State:

"1" - Indicates error to configure for reasons of failure to find the sync word within the Configuration WatchDog timer (CWDT) count, invalid IDCODE, or CRC error. See the BOOTSTS register for the specific cause of failure. INIT_B is pulled low and SWWD (SyncWordWatchDog)_strikeout goes high.

"0" - Normal configuration.

SYNC word not found (Spartan-3A)

Power-Up State: "0"

Post-Config State:

"0" - Sync Word has been properly received by the device.

"1" - Does not receive Sync Word. Usually there is an SI or double-clocking issue. Incorrect hardware connection makes the device miss the Sync Word as well.

Boot History Status Register (BOOTSTS)

This register can only be reset by POR, asserting PROGRAM_B, or issuing a JPROGRAM instruction. It is not reset by an IPROG command, because the purpose of this register is to store the result of a MultiBoot operation. At EOS or an error condition, status (_0) is shifted to status (_1), and status (_0) is updated with the current status. The default power-up state for all fields in this register is 0, indicating no error, fallback, or valid configuration detected.

VALID_0/1 - ERROR OR END OF STARTUP (EOS) DETECTED (Virtex-6, Virtex-5, Spartan-6)

"1" - At EOS or error condition. Status (_0/_1) is valid (completed configuration or error condition has been detected).

"0" - At Power-Up state.

FALLBACK_0/1 - FALLBACK TRIGGERED RECONFIGURATION (Virtex-6, Virtex-5, Spartan-6)

"1" - In Virtex-6 or Virtex-5, device falls back to the default reconfiguration, RS [1:0] actively drives 2'b00. In Spartan-6, device falls back to the golden bitstream.

"0" - Normal configuration or at Power-Up state.

IPROG_0/1 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION (Virtex-6, Virtex-5)

"1" - The internal PROG triggers configuration.

"0" - Normal configuration or at Power-Up state.

WTO_ERROR_0/1 - WATCHDOG TIME OUT ERROR (Virtex-6, Virtex-5, Spartan-6)

"1" - Watchdog time-out error occurs.

"0" - Normal configuration or at Power-Up state.

ID_ERROR_0/1 - FPGA DEVICE IDCODE ERROR (Virtex-6, Virtex-5, Spartan-6)

"1" - IDCODE error.

"0" - Normal configuration or at Power-Up state.

CRC_ERROR_0/1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR (Virtex-6, Virtex-5 or Spartan-6)

"1" - CRC error occurs.

"0" - Normal configuration or at Power-Up state.

WRAP_ERROR_0/1 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR (Virtex-6, Virtex-5)

"1" - BPI address counter wraparound error occurs.

"0" - Normal configuration or at Power-Up state.

HMAC_ERROR_0/1 - HMAC ERROR (Virtex-6)

"1" - HMAC error occurs.

"0" - Normal configuration or at Power-Up state.

RBCRC_ERROR_0/1- Readback Error (Virtex-5)

"1" Readback error cause reconfiguration.

"0" - Normal configuration or at Power-Up state.

STRIKE_CNT [15:12] (Spartan-6)

The bits record the strike count.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34104 Configuration Design Assistant N/A N/A
AR# 34909
Date Created 04/09/2010
Last Updated 02/22/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less