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AR# 34923 MIG Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Design Signal and Parameter Descriptions

Description

This section of the MIG Design Assistant describes the signals and parameters for the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Core Architecture Signal and Parameter descriptions:
  • The User Interface signals and their descriptions can be found under the "Core Architecture" -> "User Interface" section in UG406.
  • The Native Interface signals and their descriptions can be found under the "Core Architecture" -> "Native Interface" section in UG406.
  • The Physical Interface signals and their descriptions can be found under the "Core Architecture" -> "Physical Interface" section in UG406.
  • The Configuration Parameters and their descriptions can be found under the "Customizing the Core" sections in UG406.
  • MIG Virtex-6 FPGA DDR2/DDR3 SDRAM Debug Signals and Parameter descriptions:
    • For a list of signals and parameters of interest for debugging simulations please check out the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs" -> "Simulation Debug" section in UG406.
    • The PHY Later Debug Signals and their descriptions can be found under the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Hardware Debug" -> PHY Layer Debug Port" section in UG406.

    Virtex-6 FPGA Memory Interface Solutions User Guide (UG406):
    http://www.xilinx.com/support/documentation/ipinterconnect_mig-v6s6.htm

    Additional Information
    (Xilinx Answer 40462) MIG 7 Series and Virtex-6 DDR2/DDR3 - How are CAS Latency (CL) and CAS Write Latency (CWL - DDR3 only) determined?

    Linked Answer Records

    Master Answer Records

    Answer Number Answer Title Version Found Version Resolved
    34243 Xilinx MIG Solution Center N/A N/A

    Child Answer Records

    Answer Number Answer Title Version Found Version Resolved
    43879 7 Series MIG DDR3/DDR2 - Hardware Debug Guide N/A N/A

    Associated Answer Records

    Answer Number Answer Title Version Found Version Resolved
    34905 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Reordering Memory Controller N/A N/A
    34718 MIG Virtex-6 DDR2/DDR3 - PHY Architecture N/A N/A

    Actions

    AR# 34923
    Date Created 05/21/2010
    Last Updated 02/07/2013
    Status Active
    Type Solution Center
    Devices
    • Virtex-6 CXT
    • Virtex-6 HXT
    • Virtex-6 LX
    • More
    • Virtex-6 LXT
    • Virtex-6 SXT
    • Less
    IP
    • MIG
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