"> AR# 34946: MIG Design Assistant - Virtex-6 DDR2/DDR3 - DFI Interface


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AR# 34946

MIG Design Assistant - Virtex-6 DDR2/DDR3 - DFI Interface


This section of the MIG Design Assistant focuses on the DFI Interface of the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


There is the DFI Interface is the interface between the Physical Layer and the Memory Controller, and there is the User or Native Interfaces which interface between the Memory Controller and the User Design.

More specifically, the DFI Interface is the interface between the Arbiter in the Memory Controller and the Physical Layer which receives requests to send commands to the DRAM array from the bank machines. Row commands and column commands are arbitrated independently. For each command the arbiter selects a row and a column command to forward to the physical layer using a round-robin protocol.

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Associated Answer Records

AR# 34946
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG
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