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AR# 34966

Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.7 - Configurations using EMAC0 and EMAC1, each with tri-speed GMII and standard clocking, fail in Map due to Place error

Description

When both EMAC0 and EMAC1 are configured for tri-speed GMII, and the standard clocking scheme is used in both cases (neither Clock Enable nor Byte PHY are selected), Place will produce one of the following error messages.

ERROR:Place:592 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair.
or
ERROR:Place:382 - The placer was unable to find a feasible solution for the IOBs in your design.

This issue occurs because more than ten global clocks are used for the selected configuration, the maximum allowable by the Virtex-5 architecture for a given clock region. Two solutions exist.

Solution

Use an alternate clocking scheme, either Clock Enable or Byte PHY, for one or both of the EMACs to reduce global clock utilization and thus avoid the placement error.

If the standard clocking scheme must be used, replace eligible BUFGs with BUFRs where possible. The eligible BUFGs are indicated in Figure 6-8 of the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide (UG194).

AR# 34966
Date Created 03/29/2010
Last Updated 03/29/2010
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
Tools
  • ISE Design Suite - 11.5
IP
  • Virtex-5 Embedded Tri-Mode Ethernet MAC
  • Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper