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AR# 34972

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.4, which was released in ISE DesignSuite 12.1, andincludes the following:
  • General Information
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information
  • Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
  • Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
  • Provides a FIFO-based example design
  • Provides a demonstration testbench for the selected configuration
  • (Xilinx Answer 33593) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Frequently Asked Questions (FAQ)
New Features
  • ISE 12.1 software support
Resolved Issues
(Xilinx Answer 33362) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations

Known Issues
(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements
(Xilinx Answer 36223) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - When targeting SGMII or 1000BASE-X, DRC error is seen regarding GTX POWER_SAVE
AR# 34972
Date Created 04/19/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 12.1
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper