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Serial RapidIO v5.4 - Virtex-6/Spartan-6 Cores have Block RAM set to WRITE_FIRST mode which could cause collisions in hardware

AR# 34994

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Topic RapidIO
Last Updated 03/31/2010
Status Active
Description

The Block RAM used in the Virtex-6 and Spartan-6 FPGA Serial RapidIO v5.4 Buffer Cores are set to READ_FIRST mode. If the buffer is clocked asynchronously, this violates the block RAM rules and could cause collisions in hardware.

Solution

The Virtex-6 and Spartan-6 FPGA Cores are pre-production in v5.4 and should not be used in production designs. All block RAM are switched to WRITE_FIRST mode starting in v5.4 Rev1. For more information, see (Xilinx Answer 33312).
Applies To

IP

  • RapidIO Logical (I/O) and Transport Layer Interface Core
  • RapidIO Physical Layer Interface Core
 
 
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