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AR# 34995 11.5 PlanAhead - IOPL drc error when placing a clock on a N site of a GCLK pin pair.

Description

When placing a clock on a N side of the GCLK pin pair in a Spartan 6 FPGA, PlanAhead issues the following DRC error:

I/Os placed on disallowed sites -

Single ended global clock terminal mii_tx_clk drives a global clock buffer. For proper functioning, this terminal needs to be placed on the P side of a differential package pin. This terminal, placed at C9 violates this requirement

Solution

This is a known issue in PlanAhead for Spartan-6 FPGA. Clocks can be placed on the N-side of a global clock pin pair for this architecture. This issue is fixed in the next release of PlanAhead.

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AR# 34995
Date Created 04/06/2010
Last Updated 04/06/2010
Status Active
Type
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