^
Advanced Search

AR# 35000 Design Assistant for PCI Express - What happens if the power if the FPGA is re-configured, power is removed, or card removed during normal operation of the link

Description

This answer record contains the details for removing the power from an Endpoint or re-configuring the device and its affects.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express. The Xilinx Solution Center for PCI Express is
available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center forPCIe to guide you to the right information.

Solution

If power is removed from the FPGA without going through the proper power down procedure, it could cause a system crash or hang. This is due to the fact that the host may have outstanding read requests sent to the endpoint and if the endpoint does not respond, it will cause a completion timeout to occur described in (Xilinx Answer 35034). If power is applied again, most systems will link train again, but will not enumerate and configure the endpoint. A reset would be required.

Similar problems could occur if the FPGA is reconfigured, but the system is not reset. See (Xilinx Answer 34871).

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35034 Design Assistant for PCI Express - Completion Timeouts Cause the System to Freeze N/A N/A
35033 Design Assistant for PCI Express - Device is recognized by system, but problems occur N/A N/A
34871 Design Assistant for PCI Express - Using JTAG to Configure the Device N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 35000
Date Created 08/06/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
Feed Back