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AR# 35017

12.1 Project Navigator - Create instantiation template results in "WARNING:HDLParsers:3498 - No primary, secondary unit in the file ""..."


When I attempt to view the instantiation template for a VHDL file with verilog core sub-modules, the following errors occur:
"WARNING:HDLParsers:3498 - No primary, secondary unit in the file "<FILE>". Ignore this file from project file "<PROJECT>"."
"ERROR:HDLParsers:3528 - "<FILE>" Line 50. Non-printing character is not allowed in extended identifier."


The template generator is failingto recognize the mixed language syntax.
To work around this error, remove all Verilog core modules from the project, or create a new project with just the VHDL file for which you want to create a template.
This issue has been resolved in ISE Design Suite 12.2.
AR# 35017
Date 12/15/2012
Status Archive
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
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  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
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