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AR# 35032

11.2 Place - ERROR:Place:1206 - This design contains a global buffer instance


When implementing my design in a Spartan-6 FPGA, device placement fails with the following error message. What is the Clock Forwarding technique mentioned in the message, and what are the advantages of this technique?

ERROR:Place:1206 - This design contains a global buffer instance,<U_9_CLK_16_BUFG>, driving the net, <CLK_16>, that is driving the following (first 30) non-clock source pins off chip. < PIN: USB_IFCLK.O; >

This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution: instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to .C1. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue. Although the net may still not route, you will be able to analyze the failure in FPGA_Editor. < PIN "U_9_CLK_16_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;


This error message occurs when the clock placer detects that a global clock is driving an output pad through the data pin. This non-clock path is susceptible to both clock skew and routability issues. The Clock Forwarding technique switches the clock load pin from the data pin to the clock pin not only reducing the skew but also removing the routing resource limitation. For more information on routing resource limitation see (XIlinx Answer 33025).

To configure the Clock Forwarding technique, instantiate an ODDR with the D0 attached to VCC and D1 attached to GND. Connect the clock signal to the C0 clock input pin of the ODDR and the the inverted clock to C1. The Q pin of the ODDR is connected to a output pad. At the rising edge of C0, the value of D0 (VCC) will be seen on the output. At the rising edge of C1 , the value of D1 (GND) is on the output. This will produce a forwarded clock out at the output pin.

The following is a schematic representation of the Clock Forwarding circuit.

AR# 35032
Date Created 04/01/2010
Last Updated 04/01/2010
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.2