UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35034

Design Assistant for PCI Express - Completion Timeouts Cause the System to Freeze

Description

This article discusses that completion timeouts may result in system hangs.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

The most common cause of a system hang or freeze is due to a completion timeout occurring on the host. In other words, the root complex issued a read to the endpoint and the endpoint does not return a completion.

The user needs to ensure the application is draining incoming packets and returning completions for any Non-Posted packets. In most cases these will be memory reads.

If a completion timeout is expected, use ChipScope analyzer on the user application interface to ensure completions are being returned for received memory reads.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 35034
Date Created 08/06/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )