How do I use the two vid_enable output pins on the Display Port Sink core?
The data sheet says that there is only one vid_enable output, but when generating the sink core, there are two outputs.
The Display Port Sink v1.1 does have two vid_enable bits. Their behavior varies on how the core is configured.
If the user has USER_PIXELWIDTH = 1 and FORCE_DUAL_PIXEL = '0', then the vid_enable is the active signal. The user should never set USER_PIXEL_WIDTH = 1 and FORCE_DUAL_PIXEL ='1'.
If the user has USER_PIXEL_WIDTH = 2 and FORCE_DUAL_PIXEL = '1', then both vid_enable signals will assert at the same time. If the FORCE_DUAL_PIXEL = '0' when USER_PIXEL_WIDTH = 2, then the vid_enable bits may toggle independently and thus we do not recommend this configuration.
Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP Display Port Release Notes and Known Issues.