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AR# 35040

LogicCORE IP Video Direct Memory Access v1.0 - Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

Description

Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

Solution

This is a known problem that only affect the pCore interface and is addressed in the next release of the Video Direct Memory Access IP.


You can contact Xilinx Technical Support for a way to work around this issue.



Why Please see (Xilinx Answer 33256) for a detailed list of LogiCORE Video Direct Memory Access Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33256 LogiCORE IP Video Direct Memory Access (VDMA) - Release Notes N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33256 LogiCORE IP Video Direct Memory Access (VDMA) - Release Notes N/A N/A
AR# 35040
Date Created 05/26/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Video DMA