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AR# 35042

14.x Timing - Why am I unable to constrain paths to ICAP or other sites?

Description

I have attempted to constrain paths to and from the ICAP component in my design with PERIOD, FROM:TO, and TPSYNCs. However, none of these are working. Why?

The ICAP component does not have accurate timing modeled for Virtex-4, Virtex-5, and Spartan-3 devices. These architectures' speedfiles are already in production, thus changing these is a very hard process to complete.

The ICAP site is only used by a very select audience.

This limitation also applies to BSCAN, SYSMON, CAPTURE, DCIRESET, FRAME_ECC, KEY_CLEAR, STARTUP, DNA_PORT, and USR_ACCESS.

Solution

To work around this issue, use NET MAXDELAY on the nets going to and from these components.

Another way to work around this issue is to use PIN TPSYNC constraints with a FROM:TO constraint to analyzed path to and from these components.

Example:

PIN my_DNA_PORT_inst.SHIFT TPSYNC = DNA_grp;
TS01 = TO DNA_grp 10 ns;

This limitation does not exist with Spartan-6 and Virtex-6 devices. 

AR# 35042
Date Created 02/01/2011
Last Updated 08/06/2013
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
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  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • ISE Design Suite - 14.4
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
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