I have attempted to constrain paths to and from the ICAP component in my design with PERIOD, FROM:TO, and TPSYNCs. However, none of these are working. Why?
The ICAP component does not have accurate timing modeled for Virtex-4, Virtex-5, and Spartan-3 devices. These architectures' speedfiles are already in production, thus changing these is a very hard process to complete.
The ICAP site is only used by a very select audience.
This limitation also applies to BSCAN, SYSMON, CAPTURE, DCIRESET, FRAME_ECC, KEY_CLEAR, STARTUP, DNA_PORT, and USR_ACCESS.
To work around this issue, use NET MAXDELAY on the nets going to and from these components.
Another way to work around this issue is to use PIN TPSYNC constraints with a FROM:TO constraint to analyzed path to and from these components.
PIN my_DNA_PORT_inst.SHIFT TPSYNC = DNA_grp;
TS01 = TO DNA_grp 10 ns;
This limitation does not exist with Spartan-6 and Virtex-6 devices.