It has been discovered that the clock placer is not accounting for the the fact that in the larger Spartan-6 devices (LX75/LX75T and above) the BUFPLL_MCB can only be driven by four of the six PLL_ADV sites. See
UG382, page 83, for a table documenting these restrictions. In cases where an incorrect site is chosen by the placer, the design will still run through the tools with no errors, but the MIG/MPMC design will fail calibration in hardware. A calibration failure is denoted by no assertion of the cal_done signal.