Step "D" of the DDR2 Power Up and Initialization sequence in the JEDEC specification JESD79-2F is as follows:
"Wait a minimum of 400 ns then issue precharge all command. NOP or Deselect applied during 400 ns period."
This wait period is not honored by the Spartan-6 FPGA MCB MIG controller.
In both simulation and hardware, the time between the assertion of CKE and the Precharge All command is about 20 ns instead of the requested 400 ns.
Xilinx is not aware of any consequences caused by this specification violation.
This issue has been resolved in MIG v3.5 available in ISE 12.2 software.
A patch is available to use with MIG 3.4 designs (Verilog only):