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AR# 35061 11.5 EDK, plbv46_slave - Potential BRAM collisions require EDK 12.1 for Spartan-6 production use

Description

The plbv46_slave_burst_v1_01_a, plbv46_slave_single_v1_01_a,plbv46_slave_v1_04_a, rdpfifo_v4_01_a,wrpfifo_v5_00_a and earlierversions have the potential for internal block RAM collisions documented in the "Spartan-6 FPGA Block RAM Resources User's Guide".

Solution

Collisions are only possible when the packet FIFO service is included.Other cores which depend on these coresbut do not use the packet FIFO service are not affected. No Xilinx EDK IP cores currently use the packet FIFO service and so are unaffected bythis issue.

This issue might not be reported in simulation and could cause the core to fail in hardware.In summary, core using the read or write packetFIFO serviceshould not be used for production in Spartan-6 until EDK 12.1.

For more information, see (Xilinx Answer 34533).

This issue is scheduled to be fixedto be fixed in EDK12.2.A 11.5 patch will not be available before 12.1 due to ISE dependencies.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34533 Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap N/A N/A

Actions

AR# 35061
Date Created 04/12/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
  • EDK - 11.5
IP
  • PLBv46 Slave Burst
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