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AR# 35067

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.3 - Spartan-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Description

When you target the Spartan-6 FPGA in the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII version 10.3 and earlier, under certain conditions in which addresses overlap, it is possible that the contents of the Spartan-6 FPGA block RAM can become corrupted. Additional details can be found in the Spartan-6 FPGA Block RAM User Guide (UG383):
http://www.xilinx.com/support/documentation/user_guides/ug383.pdf

This problem only exists when the core is generated with the optional fabric elastic buffer for SGMII mode for Spartan-6 devices and could result in memory collisions and erroneous behavior.

Solution

This issue has been corrected in the LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII version 10.3 rev1 and later, available starting in ISE Design Suite 11.5.

Linked Answer Records

Master Answer Records

AR# 35067
Date Created 04/05/2010
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII