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AR# 35074

MIG Virtex-6 DDR2/DDR3 - Will calibration fail during Read Leveling Stage 1?

Description

When simulating or running an implemented design in hardware, the MIG Virtex-6 DDR2/DDR3 design might fail calibration for various reasons such as improper board layout or an incorrect pin-out. The calibration algorithm has two stages of read-leveling calibration. However, if a failure is seen, calibration always errors during stage 2 read leveling. Stage 1 does not trigger an error. A failure in read leveling stage 2 is denoted by dbg_rdlvl_done[1:0] = 01.Issues might have occurred during stage 1, but the design does not produce an error flag.

NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enables. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).

NOTE: This Answer Record is a part of the Xilinx MIG Solution Center, see(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Stage 1 read leveling always passes for 2 reasons:
  • The design does not differentiate between the case where the core is running at a relatively low frequency. In this case, one or even zero edges of the data valid eye are found when sweeping the IODELAY taps (maximum of 32 taps). One or zero edges can be found both in low frequency cases as well as when there are issues on the PCB. As an example, when one particular bit is stuck-at-1 or 0 no edges of the data valid eye are found. In this case, the read leveling logic would assume that the interface is running at a sufficiently low frequency where 32 taps is simply not enough to find the edge of the window, and attempts to do the best it can to calibrate with maximum margin.
  • If an eye is found, but it is "extremely" small relative to the operating frequency, the read leveling logic does not flag this as an error.
Debug of both read leveling Stage 1 and 2 should be analyzed when dbg_rdlvl_done = 2'b01; see (Xilinx Answer 35169).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35183 MIG Virtex-6 DDR2/DDR3 - Debugging Read Leveling Stage 1 N/A N/A
AR# 35074
Date Created 05/17/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG