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AR# 35078

13.3 MAP-"ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair"

Description

The following error occurs during Placement.

How do I solve this problem?

ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk2>is placed at sitet;IOB_X1Y38>. The corresponding
BUFGCTRL component<clk2_BUFGP/BUFG; is placed at site<BUFGCTRL_X0Y1>. The
clock IO can use the fast path between the IOB and the Clock Buffer if a) the
IOB is placed on a Global Clock Capable IOB site that has the fastest
dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local
Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its
half of the device (TOP or BOTTOM). You may want to analyze why this problem
exists and correct it. If this sub optimal condition is acceptable for this
design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
demote this message to a WARNING and allow your design to continue. However,
the use of this override is highly discouraged as it may lead to very poor
timing results. It is recommended that this error condition be corrected in
the design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "clk2" CLOCK_DEDICATED_ROUTE = FALSE; >

Solution

There are some dedicated fast routing resources from Global Clock Capable (GC) IOB and Local Clock Capable (CC) IOB to the global clock buffers (BUFGCTRL) and DCM/PLL/MMCM in order to obtain short delays on clock nets and better performance of the design.

This error occurs when the clock nets do not use these fast paths but use local routings which may lead to poor timing results.
 
Typically, these dedicated fast routing resources are between:
 
  1. GC IOB pair (differential)/P side of the GC IOB pair (single-ended) and BUFGCTRL
  2. CC IOB pair (differential)/P side of the CC IOB pair (single-ended) and some BUFGCTRL sites (refer to the Clocking Resources User Guide of the device family)
  3. GC IOB pair (differential)/P side of the GC IOB pair (single-ended) and DCM/PLL/MMCM
  4. CC IOB pair (differential)/P side of the CC IOB pair (single-ended) and some DCM/PLL/MMCM sites (refer to the Clocking Resources User Guide of the device family)
  5. Other clocking components. Refer to the Clocking Resources User Guide of the device family.
     

There are detailed descriptions in the error message that describe what situations that lead to the sub optimal routing. 

To solve this error, check the following.

  1. If this is not a GC or CC IOB, try changing to use a GC or CC to use the dedicated fast routing.
    • If the clock input pad is not able to be changed on the PCB, set the CLOCK_DEDICATED_ROUTE constraint as mentioned in the error message in UCF to allow non-dedicated routing.
    • If it is a connection between General IOB and the DCM/PLL/MMCM, add a BUFG between them.
    • Be aware that the non-dedicated routing leads to long delay on the clock path. This may introduce bad timing performance. Check your timing report to see if your timing requirements are met.
  2. If this is a GC or CC IOB, this error may be caused by a limitation to BUFGCTRL or DCM/PLL/MMCM sites available.
    • Check the clocking structure and resources in your design in PlanAhead or FPGA Editor and try to lock down the BUFGCTRL/DCM/PLL/MMCM in order to use dedicated clock routing as much as possible.
      Temporarily setting the CLOCK_DEDICATED_ROUTE constraint in UCF file makes MAP complete so that you can open the mapped design in FPGA Editor for analysis.
    • If there is no BUFGCTRL/DCM/PLL/MMCM site available to use the dedicated routing, set the CLOCK_DEDICATED_ROUTE constraint in the UCF constraints file to allow non-dedicated routing.
    • If it is a connection between CC IOB and the DCM/PLL/MMCM using non-dedicated routing, add a BUFG between them.
    • Be aware that the non-dedicated routing leads to long delay on the clock path. This may introduce bad timing performance. Check your timing report to see if your timing requirements are met.

 

AR# 35078
Date Created 04/06/2010
Last Updated 10/22/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite - 14
  • ISE Design Suite - 13
  • ISE Design Suite - 12