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AR# 35085

MIG Virtex-6 DDR2/DDR3 - Design Requirements for Spanning FPGA Banks


The Bank Selection screen in the MIG tool uses bold black vicinity boxes to outline the available banks from which to select Address/Control, Data, and System Clock groups. What determines the vicinity box? What determines the banks that I can select for my memory interface?

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The MIG design must be placed within three "H-Rows" (horizontal rows of FPGA banks) due to the design's use of regional clocks. For more information on the clocking structure of the MIG design, please see the Core Architecture > PHY section of UG406.

The Address/Control group is selected first as this locks the placement of the MMCM (in the same row). After Address/Control is selected, the data groups must be selected within the 3 row range.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34308 MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met N/A N/A
AR# 35085
Date Created 05/18/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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