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AR# 35087 SP605 User Guide (UG526) - Discrepancies in Pinouts between User Guide and Schematics

Description


The FPGA pin locations for the FMC connector (Table 1-28 in v1.1.1 of UG526) indicate that the J63 LPC FMC pins G6 (net FMC_LA00_CC_P) and G7 (net name: FMC_LA00_CC_N) are tied to pin locations H10 and H11 respectively on the XC6SLX45T FPGA. However, the schematics indicate that these nets are tied to ball numbers G9 and F10 respectively on the FPGA.

The FPGA pin locations for the FPGA On-Chip (OCT) Termination External Resistor Requirements (Table 1-4 in v1.5 of UG526) indicate that the ZIO and RZQ pins are tied to pin locations P3 and L6 respectively on the XC6SLX45T FPGA. However, the schematics indicate that these nets are tied to ball numbers M7 and K7 respectively on the FPGA.

Which of these two documents is correct, and when will this discrepancy be resolved?

Solution


The SP605 Hardware User Guide (UG526) is incorrect. The schematics are correct.

In the case of the FMC pins, J63 LPC FMC pins G6 (FMC_LA00_CC_P) and G7 (FMC_LA00_CC_N) are tied to pin locations G9 and F10 respectively on the XC6SLX45T FPGA. This documentation discrepancy has been addressed in v1.3 of UG526 (June 2010).
In the case of the OCT Termination resistor requirements, ZIO and RZQ are tied to pin locations M7 and K7 respectively on the XC6SLX45T FPGA.
This documentation discrepancy will be addressed in v1.6 of UG526 (July 2011).

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AR# 35087
Date Created 04/06/2010
Last Updated 07/11/2011
Status Active
Type
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