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AR# 35109 SPI-4.2 v10.1 - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.1 Core, released in ISE Design Suite12.1 and contains the following information:
  • New Features
  • Bug Fixes
  • General Information
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features in v10.1
  • ISE 12.1 software support
  • Spartan-6 device support
Bug Fixes in v10.1
  • (Xilinx Answer 34251) - Block RAM count in data sheet is not accurate for Virtex-6 FPGA
  • (Xilinx Answer 34491) - Static Alignment could intermittently fail to go in-frame
  • (Xilinx Answer 33579) - SrcTriStateEn does not tri-state TDCLK
  • Core GUI for Virtex-5 FPGA does not have 1.1 Gb/s speed selection for -3 speed grade

General Information
  • (Xilinx Answer 32917) Virtex-6 FPGA change to HIGH_PERFORMANCE_MODE attribute for IODELAYE1 elements in UCF
  • If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the Multiple Core Instantiation section under the Special Design Considerations chapter of the SPI-4.2 User Guide.
  • (Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
  • (Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?
  • (Xilinx Answer 32942) Changing static configuration signals in-circuit

Known issues in v10.1
  • Spartan-6 FPGA solutions are pending hardware validation
  • (Xilinx Answer 34629) - Spartan-6 FPGA example design might fail timing on RStat pins
  • (Xilinx Answer 35178) - Timing fails with Component Switching Limits checks for Virtex-5 devices
  • (Xilinx Answer 35270) - SPI-4.2 & SPI-4.2 Lite - Documentation does not describe behavior when partial credit is written
  • Sink DPA Clock Adjustment option for Global Clocking Mode is not supported for Virtex-6 devices
  • (Xilinx Answer 38214) - SPI-4.2 v10.1 and v10.2 - Missing constraints in ucf file when targeting Virtex-6
  • (Xilinx Answer 37553) - SPI-4.2 v10.1 - Certain Spartan-6 devices do not have enough pins in half banks for source core TX LVDS outputs

Constraints and Implementation Issues
  • (Xilinx Answer 20000) - When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21439) - When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21320) - When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21363) - PAR has problems placing components or completely routing the SPI4.2 design in my design
  • (Xilinx Answer 20280) - Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O
  • (Xilinx Answer 20040) - Timing Analyzer (TRCE) reports "0 items analyzed"
  • (Xilinx Answer 20319) - When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild

General Simulation Issues
  • (Xilinx Answer 24026) - When I run simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest
  • (Xilinx Answer 21319) - When I run timing simulation on an SPI-4.2 design example, several "TDat Error: Data Mismatch" messages are reported
  • (Xilinx Answer 21321) - Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;
  • (Xilinx Answer 21322) - When I run timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur
  • (Xilinx Answer 20030) - When I simulate an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation
  • (Xilinx Answer 15578) - When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur
  • (Xilinx Answer 35266) - NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level <top-level> <sdf name>, line <number>.

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
37553 SPI-4.2 v10.1 - Certain Spartan-6 devices do not have enough pins in half banks for source core TX LVDS outputs N/A N/A
35178 SPI-4.2 v10.1 - Timing fails with Component Switching Limit Checks for Virtex-5 devices N/A N/A
34629 SPI-4.2 - Spartan-6 FPGA example design might fail timing on RStat pins N/A N/A
38214 SPI-4.2 v10.1 and v10.2 - There are missing constraints in UCF file when targeting a Virtex-6 device N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34629 SPI-4.2 - Spartan-6 FPGA example design might fail timing on RStat pins N/A N/A

Actions

AR# 35109
Date Created 05/03/2010
Last Updated 05/22/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 12.1
IP
  • SPI-4 Phase 2 Interface Solutions
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