The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (i.e., Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does. The MIG Vitrex-6 design uses two clocks in the data capture of a DQS byte- Capture Clock and Resynchronization Clock.
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An MMCM uses the input system clock to generate the capture clock(s) and resynchronization clock(s) using the CLKPERF output. This CLKPERF output is a low jitter clock source that goes directly from the MMCM to the I/O without using a buffer. This MMCM is located in the infrastructure.v/.vhd module in the output 'rtl/ip_top' directory. The MMCM CLKPERF output is routed to OSERDES/IODELAY elements.These IODELAY elements drive BUFIO (capture logic) and BUFR (resynchronization logic) local clock buffers to create the CPT and RSYNC clocks. The IODELAYs allow each of these clocks to be adjusted individually to provide for reliable capture of the read data eye from the memory.
For a view of this capture/rsync logic, see the PHY Clocking Architecture figure (Figure 1-47) in theVirtex-6 FPGA Memory Interface Solutions User Guide. For more information on this logic, see the DDR2 and DDR3 Memory Interface Solution > Core Architecture > PHY section in theVirtex-6 FPGA Memory Interface Solutions User Guide.