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AR# 35115 Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Transmitting memory writes eventually introduces corrupt payload

Description

Known Issue: v1.4, v1.3, v1.2, v1.1

After transmitting several large memory write transactions, the write payload may be corrupted. This only happens with the VHDL version of the wrapper files

Solution

This is a known issue with the VHDL version of the wrapper source files and is scheduled to be fixed in the v1.4 release. This will not happen when using the Verilogwrapper source files.The root cause of this issue is incorrect addressing to the transmit BRAM interfacing with the integrated block. This problem can be fixed by modifying the CALC_TX_COLS and CALC_RX_COLSfunctions in the pcie_bram_top_s6.vhd module found in the source directory.

Change the CALC_TX_COLS function from:

-- Determine number of BRAM columns from total bytes
if (BYTES_TX <= 2048) then COLS_TX := 1;
elsif (BYTES_TX <= 4096) then COLS_TX := 2;
else COLS_TX := 4; -- BYTES_TX <= 8192
end if;

to:

-- Determine number of BRAM columns from total bytes
if (BYTES_TX <= 2048) then COLS_TX := 1;
elsif (BYTES_TX <= 4096) then COLS_TX := 2;
elsif (BYTES_TX <= 8192) then COLS_TX := 4;
else COLS_TX := 9;
end if;

Change the CALC_RX_COLS function from:

-- Determine number of BRAM columns from total RAM size
if (LIMIT <= 512) then COLS_RX := 1;
elsif (LIMIT <= 1024) then COLS_RX := 2;
else COLS_RX := 4; -- LIMIT <= 2048
end if;

to:

-- Determine number of BRAM columns from total RAM size
if (LIMIT <= 512) then COLS_RX := 1;
elsif (LIMIT <= 1024) then COLS_RX := 2;
elsif (LIMIT <= 2048) then COLS_RX := 4;
else COLS_RX := 9;
end if;

Revision History:
10/26/2010 - Updated for ISE 12.3 and v1.4
04/23/2010 - Updated for ISE v12.1 and v1.3
4/7/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35180 Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA N/A N/A
33277 Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3 N/A N/A

Actions

AR# 35115
Date Created 04/20/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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