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AR# 35116

MIG - Virtex-6 - DDR2/DDR3 - ISERDES Mode Usage

Description

The Virtex-6 ISERDES has several different clocking modes thataffect how you can use and drive clock inputs.The Virtex-6 DDR2/DDR3 design uses MEMORY_DDR3 mode for the ISERDES.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Use theMEMORY_DDR3 mode to support the capture of the DDR2/DDR3 data when using a free-running clock.This mode has a divide-by-2 circuit for the CLK input, which then drives an intermediate rank of flops within the ISERDES.Here, the data is captured with the capture clock and subsequently transferred to the PHY layer clock domain via the resynchronization clock.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35119 MIG Virtex-6 DDR2/DDR3 PHY - DQ I/O Structure N/A N/A
AR# 35116
Date Created 06/27/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG