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AR# 35129

MIG Virtex-6 DDR2/DDR3 - Read Leveling Stage 2


Read Leveling Stage 2 is a stage performed by the Virtex-6 MIG DDR3/DDR2 PHY during initial calibration.The purpose of the stage is to align the captured data word in the resynchronization clock domain.This calibration stage is performed in simultaneously with Write Calibration (DDR3 Only).

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


By aligning the captured data word in the rsync clock domain, the design:
  • Accounts for skew between different DQS Groups (Each DQSGroup must be within 3 clock cycles from the other DQS Groups)
  • Determines the time between when a read command is issued to the PHY and when the corresponding read data is returned to the controller
Read Leveling Stage 2 also performs bit slip on the capture data when needed. During Read Leveling Stage 2, multiple writes and reads using the same data pattern (FF00AA5555AA9966) are performed to align write calibration and read calibration properly.The writes are shifted while on the read side bitslip and alignment occurs for different bytes.

Additional Information:

  • For detailed information on Read Leveling Stage 2, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section in UG406.
  • For information on debugging calibration errors/failures, please see (Xilinx Answer 34743).
  • For more information on the resynchronization clock, please see (Xilinx Answer 34540).
  • For more information on the full series of calibration steps, please see (Xilinx Answer 34740).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34743 MIG Virtex-6 DDR2/DDR3 - Debugging Calibration Failures N/A N/A
34740 MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration N/A N/A
AR# 35129
Date Created 05/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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