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AR# 35138

SPI-4.2 Lite v5.2 - Release Notes and Known Issues for ISE Design Suite 12.1


This Release Note and Known Issues Answer Record is for the SPI-4.2 Lite (POS-PHY L4) v5.2 Core, released in ISE Design Suite 12.1, and contains the following information:

  • New Features
  • Bug Fixes
  • General Information
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


Important Note: The SPI-4.2 Lite v5.2 core is discontinued in 12.1, and will not be visible in the main CORE Generator tool catalog. You must check the "All IP Versions" check box in order to view, customize and generate the discontinued Core.

New Features

  • ISE 12.1 software support
  • Virtex-6 -1L FPGA support

Bug Fixes

General Information

  • Virtex-6 FPGA CXT devices are supported with the following performance:
    -1 speed grade: up to 400 Mb/s
  • Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the Multiple Core Instantiation section under the Special Design Consideration chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration.
  • (Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?
  • (Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?

Known Issues

  • (Xilinx Answer 35270) - SPI-4.2 & SPI-4.2 Lite - Documentation does not describe behavior when partial credit is written

Constraints and Implementation Issues

  • DDR mode is not supported in Banks 0 and 2 (top and bottom) in the Spartan-6 LX16 ES device. This only applies to "ES" devices and is fixed in Production Silicon.

    Please see the Silicon Spartan-6 FPGA LX16 CES Errata for further information:
  • (Xilinx Answer 22009) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear
  • (Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear
  • (Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through BitGen, several "WARNING" messages appear
  • (Xilinx Answer 22011) There are missing example constraints in the UCF file
  • (Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported"

General Simulation Issues

Hardware Issues

  • (Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.
AR# 35138
Date Created 04/19/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
  • ISE Design Suite - 12.1
  • SPI-4 Phase 2 Interface Solutions