SPI-3 Link Layer v7.2 - Release Notes and Known Issues for ISE Design Suite 12.1
Description
This Release Notes and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v7.2 Core (released in ISE Design Suite 12.1) and the v7.2 rev1 Core (released as a patch below), and contains the following information:
- New Features
- Bug Fixes
- General Information
- Known Issues
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Solution
New Features- ISE 12.1 software support
- Spartan-6 -3 device support
- (Xilinx Answer 34526) Spartan-6 FPGA core should not be used in production due to potential block RAM memory collision
- (Xilinx Answer 34264) Virtex-6 FPGA block RAM resource utilization in 11.4 data sheet is not accurate
- Cores configured with independent clocks and direct mode transfer flow-control might encounter hold time issues in hardware on the input DTPA bus unless one of the following conditions are met:
- Generate TX_CLK using a DCM/MMCM and select an appropriate phase shift for the system to meet timing
- Ensure the DTPA input data is already center aligned on the clock
- Transmit the data on the rising edge and then clock it into the FPGA on the falling edge
- The Tx and Rx cores are provided with default timing constraints in the UCF file generated with the core. Depending on the core configuration, target architecture, and speed grade, the core might run significantly faster. The user can modify the constraints to meet their performance requirements. As long as all timing constraints are met, the SPI-3 Link Core operates at the user specified rate. Note that the best way to verify timing closure is with user logic, rather than the example design. Implementing only the example design might artificially limit the performance of the SPI-3 Link Core (e.g., if the User Interface is routed to I/O pins).
- A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement. This solution is necessary only if the system's timing budget cannot permit the Link Core to exceed the 2 ns input requirement.
Known issues in v7.2 that are resolved in v7.2 rev1 (see patch below)
- (Xilinx Answer 38850) SPI-3 Link Layer v7.2 - Data mismatch between rdat and rx_data in Spartan-6 and Virtex-6
- (Xilinx Answer 38851) SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected
- (Xilinx Answer 38852) SPI-3 Link Layer v7.2 - Demo testbench data dropped during simulation
- (Xilinx Answer 38873) SPI-3 Link Layer v7.2 - TSX missing for first addr out of TDAT on Virtex-6 and Spartan-6 Devices
- (Xilinx Answer 34527) - SPI-3 Link Layer Core - Some designs might fail timing
- (Xilinx Answer 35266) - NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level < top-level > < sdf name >, line < number >.
Download Rev1 Update
To obtain the Rev1 update for Spartan-6 and Virtex-6 FPGAs with resolved issues described above, apply the following patch to the Xilinx ISE 12.2 or later software installation:
http://www.xilinx.com/txpatches/pub/swhelp/coregen/ar35141_spi3_link_v7_2_rev1.zip
Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.
After installing the patch, regenerate the SPI-3 v7.2 Core in the CORE Generator tool. For further information on finding the Xilinx install and using environment variables, see (Xilinx Answer 11630).
NOTE: You might be required to have system administrator privileges to install the patch if you do not have write permissions to the Xilinx Install directory.
Applies To
Design Tools
- ISE Design Suite - 12.1
IP
- SPI-3 Link Layer Interface, Multi-channel
- SPI-3 Physical Layer Interface, Multi-channel