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AR# 35153 11.4 PlanAhead - Incorrect DRC warning in relation to System Monitor auxilliary analog inputs


If any I/Os with an IOStandard other than LVCMOS25 (i.e., LVCMOS33) are locked to the bank where the System Monitor auxiliary analog I/Os are used, the PlanAhead software generates the following DRC error:

"Conflicting Vcc voltages in bank I/O Bank 13. For example, the following two terminals locked to this bank have conflicting Vccs. Signal_X of IOStandard LVCMOS33 Vcc 3.3000 & Signal_Y of IOStandard LVCMOS25 Vcc 2.5000"


This is an erroneous warning as the auxiliary analog inputs do not have an IOSTANDARD. The warning can be safely ignored.

Please note that this warning can only be ignored if in relation to the System Monitor auxiliary analog inputs. If both signals in the warning are digital inputs, the warning cannot be ignored.

For details on how to correctly setup the auxiliary inputs, see (Xilinx Answer 29240).
AR# 35153
Date Created 04/09/2010
Last Updated 10/12/2011
Status Active
Type
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