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AR# 35156

LogiCORE DDS (Direct Digital Synthesizer) Compiler v4.0 - A component switching limit is reported by PAR indicating it will not run at the requested frequency

Description

When I implement a DDS Compiler (and a clock rate greater than 400 MHz is required), a component switching limit is reported by PAR indicating it will not run at the requested frequency. Why?

Solution


The A port on the ROM used in the DDS Compiler has a  WRITE_PORT_A value which at present is set to "READ_FIRST". As this is a ROM and there is no read/write possible conflict, a "WRITE_FIRST".attribute can be assigned. However, this cannot be set via the CORE Generator GUI, so a work-around is needed.
To work around this issue, create the core with a CE port, even though the IP is running at the full clock rate. In the component instantiation, this CE port is set to high.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
29976 LogiCORE DDS (Direct Digital Synthesizer) Compiler - Release Notes and Known issues N/A N/A
AR# 35156
Date Created 07/30/2010
Last Updated 05/23/2014
Status Archive
Type Known Issues
IP
  • Direct Digital Synthesizer