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AR# 35163

MIG 7 Series and Virtex-6 DDR2/DDR3 - Per-Bit Deskew


The MIG 7 Series and Virtex-6 DDR2/DDR3 designs do not include per-bit deskew. Becauseper-bit deskewis not included, what design considerations are necessary to follow?

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Per-bit deskew algorithms are used to align each bit within a DQS group. Because this is not included, it is extremely important to follow the trace matching requirement for a DQS group:
  • The maximum electrical delay between any DQ and its associated DQS/DQS# should be 5 ps.
For full PCB Layout Guidelines, please see the DDR2/DDR3 SDRAM Memory Solution > Design Guidelines section of UG406for Virtex-6 and UG586 for 7 Series devices.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51954 MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration N/A N/A
34740 MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration N/A N/A
AR# 35163
Date Created 05/24/2010
Last Updated 09/26/2012
Status Active
Type Solution Center
  • Virtex-6
  • Virtex-7
  • Artix-7
  • Kintex-7
  • MIG 7 Series
  • MIG Virtex-6 and Spartan-6