The Virtex-6 MIG DDR2/DDR3 design is supported as it is output from the CORE Generator tool with no modifications. Xilinx does not support using the PHY stand alone only. The main reason for this support is the memory controller design includes some "PHY-like" responsibilities that are pertinent for proper operation. Additionally, Xilinx does not provide the timing requirements for the memory controller to PHY interface.
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The "PHY-Like" responsibilities performed by the DDR2/DDR3 Memory Controller are sending the periodic reads required for the phase detector circuit and sending ZQ Calibration commands in order to satisfy the JEDEC DDR3 Standard.
Common Questions on PHY Interface Signals: