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AR# 35176

CAN v3.2 - Release Notes and Known Issues for ISE 12.1

Description

This Release Notes and Known Issues Answer Record is for the Can v3.2 Core, which was released in ISE Design Suite 12.1 and contains the following information:

  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features -

  • ISE 12.1 software support
  • Support for AutomotiveSpartan-6 families

Resolved Issues

  • Virtex-6 FPGA block RAM Memory collision error. (CR 547753)
    Description: If block RAM is in SDP or TDP RF modes and there is an address collision.
  • Spartan-6 FPGAblock RAM Memory collision error. (CR 551105)
    Description: If block RAM is in SDP or TDP RF modes and there is an address collision.

Known Issues

AR# 35176
Date Created 04/15/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
Devices
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • More
  • Spartan-3A DSP
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.1
IP
  • CAN