We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35180

Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA


This Answer Record describes the Known Issues for the Spartan-6 FPGA generation used with ISE Design Suite 12.


The following represent a collection of issues that have been identified in the12.4 ISE Design Tools and are related to Spartan-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.

It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in softwareare picked up.

(Xilinx Answer 36521) Spartan-6 Configuration - BPI configuration not supported in LX25/T devices
(Xilinx Answer 39582)Spartan-6 Design Advisory- When using POST_CONFIG_CRC the INIT_B pin can not be User I/O
(Xilinx Answer 38733) Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

GTP Transceivers:
(Xilinx Answer 35237) Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk / SSO Guidelines

(Xilinx Answer 38408) Spartan-6 Design Advisory - IODELAY2 -early edge delays, late edge delays,and single data bit corruption

PCI Express:
(Xilinx Answer 37955) Spartan-6 FPGA Integrated Block Wrapper v2.1 for PCI Express - VHDL Wrapper Not Available for v2.1 Release
(Xilinx Answer 36416) Spartan-6 FPGA Integrated Block Wrapper v1.4 and v2.1 for PCI Express - User implemented configuration space registers starting addresses are not customizable

Timing Analysis:
(Xilinx Answer 39545) 12.4 - Timing Analysis -ISE 12.4 does not support Spartan-6 -3 speed grade Engineering Sample (ES) devices

Additional Resources:
(Xilinx Answer 34856) - Design Advisory for the Spartan-6 FPGA Master Answer Record
Spartan-6 Production Errata and Product Change Notification (PCN)
Improving Performance in Spartan-6 FPGA Designs White Paper(WP311)
Targeting and Re-targeting Guide for Spartan-6 FPGAs White Paper(WP309)

Revision History
12/20/2010 - Updated complete list for 12.4 Known Issues
10/05/2010 - Updated complete list for 12.3 Known Issues
07/23/2010 - Updated complete list for 12.2 Known Issues
06/16/2010 - Added Answer Records 35978, 35976, 35818, 35044, and 36221
05/19/2010 - Added "Additional Resources" section
05/03/2010 - Initial 12.1 Release

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36741 MIG v3.5, Spartan-6 MCB - Traffic Generator Data Pattern cannot be modified N/A N/A
36575 MIG v3.0-3.5, Spartan-6 MCB - Refresh period is too large N/A N/A
36475 MIG v3.0-3.4, Spartan-6 MCB - "ERROR:HDL Compiler:432 occurs when running MIG output" N/A N/A
35480 Spartan-6 PLL - Timing Analyzed Incorrectly When Using CLKOUT0 as Feedback N/A N/A
35417 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q, and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro tools N/A N/A
35397 12.2 PlanAhead - The PlanAhead tool cannot set KEEPER to an I/O port of Spartan devices N/A N/A
35345 11.5/12.1 - iMPACT - Missing option for ''Add non-configuration data files'' in Spartan-6 MultiBoot PROM file generation N/A N/A
34704 Spartan-6 - Use of the PLL DRP will result in Post Config CRC errors N/A N/A
33888 LogiCORE IP Display Port v1.2 - The example design does not meet timing when I target a Spartan-6 device. Why? N/A N/A
34046 MIG v3.3-v3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported N/A N/A
35115 Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Transmitting memory writes eventually introduces corrupt payload N/A N/A
34629 SPI-4.2 - Spartan-6 FPGA example design might fail timing on RStat pins N/A N/A
34466 ISE Design Suite 12 - Known Issues N/A N/A
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
34153 Spartan-6 FPGA MCB - Can MCB pins be swapped to help facilitate board layout? N/A N/A
36431 MIG/MPMC Spartan-6 MCB - Is there a preferred or required PLL location that should be used within the design? N/A N/A
35237 Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines N/A N/A
34533 Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap N/A N/A
AR# 35180
Date Created 04/30/2010
Last Updated 10/16/2012
Status Active
Type Known Issues
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.4