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AR# 35189

MIG Virtex-6 DDR2/DDR3 - PHY - Architecture Design

Description

The Physical interface of the Virtex-6 DDR2/DDR3 MIG include the all the IO for the address/control, data and clocking and associated logic. The initialization sequence and calibration are controlled in the PHY.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The PHY provides a physical interface to an external DDR2 or DDR3 SDRAM. The PHY generates the signal timing and sequencing required to interface to the memory device. It contains the clock-, address-, and control-generation logic, write and read datapaths, and state logic for initializing the SDRAM memory after power-up. In addition, the PHY contains calibration logic to perform timing training of the read and write datapaths to account for system static and dynamic delays.

Please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG406 for detailed information on the PHY.

For more information on the PHY architecture see the following Design Assistant Answer Records:

(Xilinx Answer 35242) - Description of Clocking and MMCM structure

(Xilinx Answer 35119)) - DQ I/O Structure

(Xilinx Answer 34480) - Phase Detector

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35119 MIG Virtex-6 DDR2/DDR3 PHY - DQ I/O Structure N/A N/A
AR# 35189
Date Created 05/21/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG