This Answer Record contains the Release Notes for the LogiCORE IP Ethernet AVB Endpoint v2.3, which was released in ISE Design Suite 12.1 and includes the following:
General Information New Features Resolved Issues Known Issues
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the
IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
General InformationThe following are Generated out of CORE Generator software: Ethernet AVB Endpoint core netlist Example design HDL top-level and associated HDL files Demonstration test bench to exercise the example design Documentation Directory containing Data Sheet, Getting Started Guide, and User Guide New Features ISE 12.1 software support QPro Virtex-6 FPGA Hi-Rel support QPro Spartan-6 FPGA Hi-Rel support QPro Virtex-5 FPGA Hi-Rel support Software configurable resets Resolved Issues (Xilinx Answer 33653) LogiCORE IP Ethernet AVB Endpoint v2.2 - When targeting Spartan-6 FPGAs, block RAM is not initialized correctly (Xilinx Answer 33654) LogiCORE IP Ethernet AVB Endpoint v2.2 - Software driver header file xavb.h does not compile (Xilinx Answer 33655) LogiCORE IP Ethernet AVB Endpoint v2.2 - Software drivers not automatically found in pcore (Xilinx Answer 33656) LogiCORE IP Ethernet AVB Endpoint v2.2 - Base Address of AVB software driver not set Known Issues
The software drivers in this release have not been updated. These will be updated for recent AVB specification changes in a future release.
The optional pcore functionality has been tested with EDK 11.3. At the time of release, this has not yet been tested with EDK 12.
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