The MIG Virtex-6 DDR2/DDR3 design includes an option to generate the core with a debug port. Enabling the debug port provides the ability to view the behavior during hardware operation of common debug signals through Chipscope. To enable the debug port, turn the Debug Signals for Memory Controller option to ON. This option is available on the FPGA Options screen of the MIG tool. Once the design is generated with this option enabled, generate a bitstream with the provided Example Design using the "ise_flow.bat" script file located in the output 'example_design/par' directory. Running the Example Design with the debug port is the first step in any hardware debug. This is a known working design which can be configured to test for many different signal integrity issues.
This Answer Record provides useful information on using the debug port to correct specific types of problems such as calibration failures and bit errors.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For a complete list of Debug Port signals, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Debugging Virtex-6 DDR2/DDR3 SDRAM Designs > Hardware Debug > Phy Layer Debug Signals within UG406.
The Debug Port is enabled through the top-level RTL parameter DEBUG_PORT. Setting this to "ON" enables the port in the RTL. Additionally, CORE Generator command lines are required in the "ise_flow.bat" script file to generate the necessary cores to run in the ChipScope analyzer.
Using the Debug Port to Debug Write Leveling:
Using the Debug Port to Debug Read Leveling Stage 1 (includes steps on calculating data valid window):
Using the Debug Port to Debug Read Leveling Stage 2:
Using the Debug Port to Isolate a Write versus Read Problem: