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AR# 35208

MIG v3.3-3.4 DDR/RLDRAMII - VHDL example design results in error about iteration limit reached

Description


I am trying to run a simulation of a Virtex-4 VHDL MIG design using the default settings.
 
I am receiving an error about an iteration limit being reached .
 
How do I work around this error?

Solution


This is an issue in the simulation test bench confirmed in DDR and RLDRAMII example designs.
 
To work around the error, modify the TRCE delays in sim_tb_top.vhd from "0.00 ns" to "0.01 ns".
 
Existing code:
 

constant  TPROP_PCB_CTRL : time := 0.00 ns; --CTRL delay value
constant TPROP_PCB_QK : time := 0.00 ns; --QK delay value
constant TPROP_PCB_DATA : time := 0.00 ns; --DATA delay value
constant TPROP_PCB_DATA_RD : time := 0.00 ns; --READ DATA delay value



Modify the parameters as below:
 

constant TPROP_PCB_CTRL : time := 0.01 ns; --CTRL delay value
constant TPROP_PCB_QK : time := 0.01 ns; --QK delay value
constant TPROP_PCB_DATA : time := 0.01 ns; --DATA delay value
constant TPROP_PCB_DATA_RD : time := 0.01 ns; --READ DATA delay value



This issue has been fixed in 12.2 MIG v3.5.
AR# 35208
Date 08/12/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less
IP
  • MIG