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AR# 35214

12.x CORE Generator - Known Issues for CORE Generator 12.x

Description

This Answer Record contains a list of known issues involvingCORE Generatorin the 12.x ISE Design Suitesoftware release(s).

For IP-specific information, see the Xilinx IP Web page:

http://www.xilinx.com/ipcenter

Solution

Outstanding Known Issues in ISE designSuite 12.3
(Xilinx Answer 20780) - CORE Generator - "ERROR:coreutil:195 - Could not create Java virtual machine"
(Xilinx Answer 21955) - An error occurred while running Java. This might be due to memory limitations
(Xilinx Answer 24389) - Tab outlines of the IP views (View by function/name/Generated) are not visible on Windows XP64
(Xilinx Answer 32251) - CORE Generation software fails when the project is using a UNC path to point to a network location
(Xilinx Answer 32320) - Issues can occur when generating/regenerating a MIG project with the same component name
(Xilinx Answer 32396) - Generating a core through Project Navigator causes example VHDL simulation files to be overwritten
(Xilinx Answer 32410) - A project file is not created when Japanese characters are used for the project name
(Xilinx Answer 32412) - Error message displays when customizing IP over Xwin32"X, " Error: BadWindow (invalid Window parameter) 3"
(Xilinx Answer 35374)- WARNING:sim:541 - Could not import file 'my_core.xco' during projectmigration.
(Xilinx Answer 35391)-View Resource Utilization option has been removed
(Xilinx Answer 36680) - Entering invalid parameters in iBERT core results in cryptic error message
(Xilinx Answer 38170) - Spartan-3 Single DCM Clockingcore does not associate with the correct architecture

Known Issuesresolved inISE designSuite 12.2
(Xilinx Answer 32486) - CORE Generator software help contains outdated information on how to obtain a Full IP license
(Xilinx Answer 35292) - IP core name cannot be changed when created through Manage Cores,in specific use case
(Xilinx Answer 35294)- IP core name validity check fails without explanationif component and internal module names match
(Xilinx Answer 35376)- Naming an IP core "coregen"results in 'ERROR:sim:608' which can be ignored
(Xilinx Answer 35378)- Import IP Core fails if the project target device is not supported by the IP being imported
(Xilinx Answer 35379)- Re-customization fails if the coefficient (.coe) file for a core cannot be found.
(Xilinx Answer 35389)- Setting the JAVA memory size from the CORE Generator GUI has no effect
(Xilinx Answer 35392)- Generating a MIG core fails from Project Navigator after generating other IP cores
(Xilinx Answer 35664)- Operational issues on old project with flow vendor = ePD


Known Issuesresolved inISE designSuite 12.3
(Xilinx Answer 35293)- 'Project Processes' fail when the process does not apply to all IP cores
(Xilinx Answer 35311)- The project working directory is set with an absolute path location

Linked Answer Records

Child Answer Records

AR# 35214
Date Created 04/26/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3