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Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit VHDL Wrapper corrupts received TLP addresses

AR# 35225

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Topic PCIe
Last Updated 07/14/2010
Status Active
Description


Known Issue: v1.5, v1.4.3, v1.4.2, v1.4.1

Under some conditions received TLPs might have an incorrect address when using the x8 Gen 2 128-bit VHDL Wrapper.

Solution


This issue is resolved in v1.5 rev 1. For the v1.5 rev 1 patch, see (Xilinx Answer 34279).

This problem does not exist in the Verilog version of the wrapper.

Revision History
07/14/2010 - Initial Release
Applies To

Devices

  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT

Design Tools

  • ISE Design Suite - 12.1

IP

  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
 
 
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