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AR# 35225 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit VHDL Wrapper corrupts received TLP addresses

Description


Known Issue: v1.5, v1.4.3, v1.4.2, v1.4.1
Under some conditions received TLPs might have an incorrect address when using the x8 Gen 2 128-bit VHDL Wrapper.

Solution


This issue is resolved in v1.5 rev 1.For the v1.5 rev 1 patch, see (Xilinx Answer 34279).
This problem does not exist in the Verilog version of the wrapper.
Revision History
07/14/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Actions

AR# 35225
Date Created 07/14/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 12.1
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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