We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35225

Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit VHDL Wrapper corrupts received TLP addresses


Known Issue: v1.5, v1.4.3, v1.4.2, v1.4.1
Under some conditions received TLPs might have an incorrect address when using the x8 Gen 2 128-bit VHDL Wrapper.


This issue is resolved in v1.5 rev 1.For the v1.5 rev 1 patch, see (Xilinx Answer 34279).
This problem does not exist in the Verilog version of the wrapper.
Revision History
07/14/2010 - Initial Release

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 35225
Date Created 07/14/2010
Last Updated 05/20/2012
Status Archive
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 12.1
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )