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AR# 35228

Bitgen:PhysDesignRules:368 - The signal is incomplete.


When running bitgen to generate a bitstream, I see messages like the one below in the log file -

ERROR:PhysDesignRules:368 - The signal <**> is incomplete. The
signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <**> is completely unrouted.\

What causes these errors?


These are valid design errors. They occur because the ports specified do not drive anything. The design should be modified to eliminate these unrouted signals. A good starting point for debug is to use FPGA Editor. To search for unrouted nets, press F2 and look at the tab that indicates routes loads/inputs and outputs etc. This may help track down some issues with the Design.

When PAR fails to successfully route all of the signals, the root cause can be one of several things including:

1. A component may be configured in such a way that it is unroutable. An example would be a Virtex-4 design with ILOGIC and OLOGIC components in adjacent sites that have different SR signals. These components share a routing resource to the SR pin, so they must use the same SR signal. Otherwise, one of the signals will be unroutable. The root cause of this problem is a MAP packing issue.

2. A component may be placed such that it is unroutable. An example would be a carry chain that is not aligned properly by the placer so that the dedicated COUT-->CIN resource can be used. The router will attempt to use a BX-->CIN route-thru, but if the slices is already using the BX pin for something else, then the carry net is unroutable. The root cause of this problem is in the placer.

3. A design may also be unroutable due to congestion. There may simply be too many connections in the design for the router to find a solution.

4. A design may be unroutable due to over-constraining of timing. The placement and routing decisions that are a compromise between routability needs and timing needs. If the timing needs are too heavily weighted, then the routability can suffer.

Alternately, you can disable Design Rule Checking in Bitgen, but this is not a recommended solution.
AR# 35228
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.1
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