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AR# 35239

LogiCORE IP XAUI v9.2 - Release Notes and Known Issues for ISE Design Suite 12.1


This Answer Record contains the Release Notes for the LogiCORE IP XAUI v9.2 Core, which was released in the ISE Design Suite 12.1,andincludes the following:
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For LogiCORE IPXAUI Frequently Asked Questions (FAQ), see (Xilinx Answer 33596).


New Features
  • 12.1 ISE Design Suite support
  • The XAUI core v9.1rev1 was the last version totarget Virtex-6 GTX CES silicon. XAUI v9.2 and later versions of the core support production silicon with production GTX attributes.

Resolved Issues
  • (Xilinx Answer 33135) LogiCORE IP XAUI v8.2 - Incorrect Virtex-6 FPGA GTX attribute when not using the IEEE state machines
  • (Xilinx Answer 33649)LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition
  • (Xilinx Answer 34163) - LogiCORE IP XAUI v9.1 - The Spartan-6 FPGA Example Design does not implement the DCM_SP attribute setting for "CLK_FEEDBACK"
  • (Xilinx Answer 34159) - LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors
  • (Xilinx Answer 33504) - Spartan-6 FPGA GTP Transceiver: Channel Bonding signals fail timing
  • (Xilinx Answer 33486) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 device GTP and Virtex-6 device GTX wrappers
  • (Xilinx Answer 33488) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated
  • (Xilinx Answer 33489) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA Example Design
  • (Xilinx Answer 33491) - LogiCORE IP XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation
  • (Xilinx Answer 33492) - LogiCORE IP XAUI v9.1 - Implementing Spartan-6 and Virtex-6 FPGA Examples Designs results in MAP errors for some device packages

Known Issues
  • (Xilinx Answer 39492) - LogiCORE IP XAUI - GTX Transceiver Delay Aligner Errata and Work-around
  • (Xilinx Answer 35591)- Spartan-6 FPGA GTP Transceiver Wizard: tx_sync module does not use appropriate wait times
  • (Xilinx Answer 35241) -LogiCORE IP XAUI v9.2 - Timeout seen in some Virtex-5 FPGA Example Design Timing Simulation
  • (Xilinx Answer 24678) - Virtex-4 FPGA GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing simulation

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
35241 LogiCORE IP XAUI v9.2 - Timeout seen in some Virtex-5 FPGA Example Design Timing Simulations N/A N/A
AR# 35239
Date Created 04/19/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
  • Virtex-4 FX
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-6 LXT
  • Less
  • ISE Design Suite - 12.1
  • XAUI